Unguarded Schottky barrier diodes with dielectric underetch at silicide interface

ABSTRACT

One embodiment of the invention relates to an unguarded Schottky barrier diode. The diode includes a cathode that has a recessed region and a dielectric interface surface that laterally extends around a perimeter of the recessed region. The diode further includes an anode that conforms to the recessed region. A dielectric layer extends over the dielectric interface surface of the cathode and further extends over a portion of the anode near the perimeter. Other devices and methods are also disclosed.

This application claims the benefit of U.S. Provisional Application Ser. No. 60/804,192, filed Jun. 8, 2006, entitled “Method for Making an Ideal PtSi Unguarded Schottky Barrier Diode,” and U.S. Provisional Application Ser. No. 60/804,195, filed Jun. 8, 2006, entitled “Method for Suppression of Hot Carrier Damage in Unguarded Schottky Barrier Diodes”; both of which are incorporated herein by reference in their entireties.

BACKGROUND

The invention relates generally to semiconductor devices and more particularly to unguarded Schottky barrier diodes.

A diode is an electrical component that allows current to flow in one direction, but not in the other. FIG. 1 is a circuit symbol of a typical Schottky barrier diode 100, where the diode 100 has an anode 102 (metal) in direct contact with a cathode 104 (n-type doped semiconductor material). In Schottky barrier diodes, conventional current can typically flow from the anode 102 to the cathode 104, but not from the cathode to the anode. Schottky barrier diodes typically result in fast switching times and low forward voltage drop, relative to conventional p-n diodes.

Schottky barrier diodes are available in guarded and unguarded diode configurations. Guarded Schottky barrier diodes include a p-n junction guard ring disposed in the substrate around the perimeter of the diode. Although the p-n junction guard ring eliminates some adverse leakage current effects around the perimeter, at higher forward bias (especially for high barrier height silicides) there is significant injection of minority carriers. This injection leads to very slow diode recovery after the forward bias is removed. This phenomenon cannot be tolerated in many high speed applications.

Therefore, many high speed applications require integrated unguarded Schottky barrier diodes to be able to operate at high reverse bias voltages while offering very fast recovery speeds. For some time, however, these diodes have suffered from hot carrier damage even after a modest reverse bias of 10-15 volts or less. This hot carrier damage can lead to unguarded Schottky barrier diodes with non-ideal I-V characteristics. Accordingly, there is a need for improved unguarded Schottky barrier diodes and manufacturing techniques.

SUMMARY

One embodiment of the invention relates to an unguarded Schottky barrier diode. The diode includes a cathode comprising a recessed region and a dielectric interface surface that extends laterally around a perimeter of the recessed region. A silicide layer at least substantially conforms to the recessed region. The diode also includes a dielectric layer having a window with sidewalls that are near the perimeter of the recessed region, and the dielectric layer extends continuously over the dielectric interface surface and at least a portion of the silicide layer near the perimeter of the recessed region.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 (Prior Art) shows a conventional circuit symbol for a Schottky barrier diode;

FIG. 2 (Prior Art) shows a conventional Schottky barrier diode that may suffer from leakage current through a metal insulator diode;

FIGS. 3A-3B show an unguarded Schottky barrier diode that may mitigate formation of a metal insulator diode at its perimeter;

FIG. 4 shows a somewhat general method of forming an unguarded Schottky barrier diode; and

FIGS. 5-12 show cross-sectional views of stages in a more detailed method of forming an unguarded Schottky barrier diode.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Aspects of this invention are aimed at preventing formation of a leaky metal insulator semiconductor (MIS) parasitic diode at the Schottky barrier diode perimeter. A more detailed description of this problem is now discussed with reference to FIG. 2, which shows an unguarded Schottky barrier diode 200 having a leaky, low-barrier height MIS diode 202 at its perimeter. In essence, the MIS diode 202 allows current to “leak” through or around the diode, which causes the overall diode characteristics to significantly deviate from those of an ideal diode.

Briefly, the diode 200 includes a lightly doped n-type silicon region cathode 204 under which a buried layer 206 (cathode contact) resides. A dielectric layer 208 is formed over the cathode 204, and a window 210 opening with tapered sidewalls 212, 214 is formed within the dielectric layer 208. A silicide layer 216 is formed in direct contact with the cathode 204 and is directly adjacent to the bottom of the tapered sidewalls 212, 214. A titanium-based (Ti-based) diffusion barrier metal layer 224 (or other refractory metal) is typically formed over the silicide layer 216, and filler metal 225 is deposited over the diffusion barrier metal layer 224.

The parasitic MIS diode 202 is formed at a perimeter 218 of the Schottky barrier diode (i.e., near the bottom of the tapered sidewalls 212, 214 of the dielectric). More particularly, the MIS diode 202 exists where a thin dielectric tail 220 is sandwiched between the diffusion barrier metal 224 and the cathode 204. Ideally, during operation, all current would flow directly between the cathode 204 and anode 216 of the diode, and not through the MIS diode 202. However, the inventors have appreciated that a sufficiently thin dielectric tail 220 allows the MIS diode 202 to conduct a significant amount of current by tunneling. This leakage current, combined with the current flowing through the anode 216 causes the Schottky barrier diode 200 to have non-ideal I-V characteristics.

Moreover, this parasitic leakage current from the MIS diode is highly variable and difficult to control. This results in poor manufacturing repeatability and poor device to device matching. Thus, diode 200 is not generally usable in high precision circuits unless the problem with the formation of the MIS diode can be prevented. Note that the MIS diode dominates the forward bias characteristics only at lower bias voltages because its high series resistance limits its current at higher forward bias voltages (i.e., the cathode 204 and anode 216 of the Schottky barrier diode have a low series resistance that does not limit the current flow at higher bias voltages).

Other aspects of this invention are aimed at suppressing hot carrier damage at the perimeter 218 of unguarded Schottky barrier diodes. Hot carrier damage can occur when charged carriers (electrons or holes) are accelerated by a high electric field present at the perimeter 218 of the diode 200. These hot carriers are injected into the dielectric 208, and damage the dielectric/silicon interface by generating charged trapping centers. Note that the electric field at the perimeter of the diode is described by the following equation:

$\begin{matrix} {{E\left( r_{j} \right)} = {{- \frac{{qN}_{D}}{2ɛ_{s}}}\left( \frac{r_{W}^{2} - r_{j}^{2}}{r_{j}} \right)}} & (1) \end{matrix}$ where E is the electric field, r_(w) is the radius of the depletion layer edge and r_(j) is the radius of the anode/cathode junction at the perimeter. Equation 1 shows that the electric field is inversely proportional to the radius r_(j).

Another element contributing to hot carrier damage is the oxide/silicon interface at the diode's perimeter (i.e., the location where hot carriers can inflict damage by creating positively charged trapping centers). The density of these charge centers is a linearly dependent function of the perimeter current and time. This charge enhances the carrier concentration at the perimeter of an n-type substrate and reduces the carrier concentration of a p-type substrate. Increase in the effective doping concentration further increases the electric field, as described in Equation 1, by increasing N_(D) in this example for an n-type silicon substrate. The effective Schottky barrier height is reduced by the barrier lowering terms below,

$\begin{matrix} {\Phi_{B}^{*} = {\Phi_{B\; 0} - {\alpha\; E} - \sqrt{\frac{qE}{4{\pi ɛ}_{s}}}}} & (2) \end{matrix}$ where Φ_(B0) is the intrinsic barrier height, and α is the tunneling coefficient (α=3 nm for PtSi). Increase in the electric field, caused by the localized increase in the carrier concentration, results in a drop of the effective Schottky barrier height at the perimeter after the reverse bias stress damage occurs. This explains why there is an increase in the reverse current after subjecting the diode to a significant reverse bias stress. The opposite effect (i.e., decrease in reverse current) is observed in diodes with a p-type silicon substrate where the localized carrier concentration decreases after the stress.

Therefore, aspects of the invention aim to prevent the formation of the MIS diode and to suppress hot carrier damage at the perimeter of the Schottky barrier diode. FIGS. 3A-3B show an example of an unguarded Schottky barrier diode 300 that may achieve these ends.

The diode 300 of FIGS. 3A-3B includes a cathode 302 having a recessed region 304 over which a silicide layer 306 is formed. A dielectric layer 308 having a window 310 therein overlies the cathode 302. To prevent the formation of an MIS diode, the silicide layer 306 is formed to undercut a portion of the dielectric layer 308 near a perimeter 312 of the recessed region 304. A diffusion barrier metal 314 (e.g., a Ti-based diffusion barrier metal or other similar refractory metal) may be formed over the silicide layer, and the remainder of the opening of window 310 may be filled with a high conductivity filler metal 315. In effect, by providing a silicide layer 306 that undercuts the dielectric layer 308, the diode 300 has significantly thick isolation between the barrier diffusion metal 314 and the cathode 302, such that current tunneling (and, thus, unwanted parasitic leakage) will not occur. In addition, because the silicide layer 306 undercuts the dielectric 308, the diode 300 has an increased anode/cathode junction radius r_(j)′ (compared to radius r_(j) of diode 220), which reduces the electric field carriers experience, thereby limiting hot carrier damage.

As shown in FIG. 3A, the cathode 302 typically overlies a highly conductive buried layer 316 (such as, e.g., a highly doped n-type region of the silicon substrate) that serves as a cathode contact.

The cathode 302, which may be a lightly doped n-type region of the silicon substrate, includes a dielectric interface surface 318 that extends laterally around the perimeter 312 of the recessed region 304. The recessed region 304 may have a recessed surface 320 and concave sidewalls 322, 324.

The silicide layer 306 may substantially conform to the recessed region 304 and, depending on the implementation, the silicide layer 306 may have various thicknesses. For example, in the illustrated embodiment, the silicide thickness T is such that a top silicide surface 326 is positioned between the dielectric interface surface 318 and the recessed surface 320. However, depending on the silicide layer thickness T and the depth d of the recessed region, the top silicide surface 326 could also be above the dielectric interface surface 318.

The dielectric layer 308 can be characterized by a window 310 opening or aperture in the dielectric layer, which has sidewalls 328, 330 that are near the perimeter 312 of the recessed region. In the illustrated embodiment, the sidewalls are generally concave, although they could be convex or substantially vertical in other embodiments. These sidewalls may cause the dielectric layer to include a tail 332 (FIG. 3B), which is a thin region of the dielectric sandwiched between the barrier diffusion metal 314 and the silicide layer 306. The extent by which the recessed region must undercut the tail 332 (length L) may be a function of the reverse bias the diode is to withstand. As the reverse bias the diode is to withstand increases, a designer may increase the length L, depth d, and/or the thickness T of the silicide layer 306. In effect, by increasing the length L, depth d, and/or thickness T, the designer is providing greater isolation between the barrier diffusion metal 314 and the cathode 302, such that unwanted parasitic leakage will not occur. The same is also increasing the effective anode/cathode radius (from r_(j) in FIG. 2 to r_(j)′ in FIG. 3B) and, thus, decreasing the electric field as described by Equation 1. For example, in one embodiment where the diode is to withstand a reverse bias of approximately 20 V, the recessed region undercuts the dielectric by a length L of approximately 10-100 nm. In various embodiments, the silicide layer may have a thickness T of approximately 10-100 nm.

Example methods for manufacturing such Schottky barrier diodes are described with reference to a general method 400 illustrated in FIG. 4 and with reference to more detailed steps of a method 500 illustrated in FIGS. 5-12. It will be appreciated that the ordering of steps is not limited by the illustrated ordering and that some acts or events may occur in different orders than illustrated and/or concurrently with other acts or events including acts or events apart from those illustrated and/or described herein. In addition, not all illustrated steps may be required to implement a methodology in accordance with one or more aspects or embodiments of the invention. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

As shown in FIG. 4, method 400 starts with providing a dielectric layer overlying a cathode in a semiconductor substrate. At 402, a window opening is etched into the dielectric layer, thereby exposing a portion of the cathode. In 404, an etch is performed to form a recessed region in the cathode. In various embodiments, blocks 402 and 404 may be performed in a single etch that results in a significant isotropic overetch at the perimeter of the diode. This overetch creates a silicon profile with a junction radius much larger than created by prior art processes. Thus, this etch leads to an unguarded Schottky barrier diode with significantly reduced electric field (relative to prior art processes), which can suppress the onset of the reverse bias induced hot carrier damage until much higher bias voltages are applied. After the recessed region is formed, in 406 a metal that is used in silicide formation is conformally deposited over the recessed region. In 408, the metal layer in the recessed region is converted to a metal silicide using a high temperature treatment. In 410, the non-silicided metal is removed. Lastly, in 412, a metal layer contact for the anode is formed.

More detailed steps in an example method 500 are described with reference to FIGS. 5-12, which show cross-sectional views of various stages in the manufacture of an embodiment of an unguarded Schottky barrier diode.

In FIG. 5, a lightly doped silicon region cathode 502 is formed over a highly doped silicon buried layer 504. The highly doped buried layer 504 may be formed, for example, by implanting a high dopant concentration of n-type impurities into a silicon substrate. This can be followed by an epitaxial growth of silicon to form the lightly doped silicon layer 502 cathode region.

In FIG. 6, a dielectric layer 600 is formed over the lightly doped silicon cathode 502. In various embodiments, the dielectric layer 600 may comprise a single layer or some combination of thermally grown SiO₂, deposited SiO₂, silicon nitride or another suitable dielectric. In various embodiments, the dielectric layer may include spacers or not, and/or may comprise a single solid material (e.g., field oxide or other continuous material).

In FIG. 7, once the dielectric layer 600 has been formed, a mask 701 (such as photoresist or a hard mask) is formed over the dielectric layer, and an etch 700 is performed to form a window 702 opening in the dielectric layer 600 through which a portion of the cathode is exposed. In some embodiments, etch 700 may be an isotropic (multidirectional) etch, such as a wet or plasma etch, that results in concave sidewalls. In other embodiments, etch 700 may be an anisotropic (unidirectional) etch, such as a plasma (RIE) etch, that results in relatively vertical sidewalls. In FIG. 8, an etch 800 is performed to form a recessed region 802 within the cathode 502. This etch 800 is typically an isotropic etch that is selective between the silicon cathode and the dielectric layer, thereby removing a portion of the cathode and undercutting the dielectric layer by length L.

In some embodiments, etches 700 and 800 could be carried out as separate etches. In other embodiments, etches 700 and 800 may be performed as a single etch, where the semiconductor structure is kept within the etch tool and not exposed to the laboratory environment. Many different single or sequential etches having different material selectivities and etch rates may accomplish similar end results. The selection of a particular etch technique depends upon fabrication capability, cost and convenience.

In FIG. 9, the mask 701 has been removed and a silicidation metal 900 has been conformally deposited over the dielectric layer 600 and the recessed region 802. This silicidation metal 900 may be deposited, for example by a sputtering process, evaporation, CVD or any other suitable technique. In one embodiment, the silicidation metal could be platinum (Pt), palladium (Pd) or cobalt (Co), although any other suitable metal could be used.

In FIG. 10, the structure is exposed to one or more high temperature treatments to convert the silicidation metal 900 that contacts the cathode to a silicide. As shown, the deposited silicidation metal 900 has now been converted to a silicided metal layer 1000 over the silicon cathode region but not over the dielectric layer 600, leaving non-silicided metal 1002 remaining over the regions not having exposed silicon. Typically, the silicide layer 1000 could be a high barrier height near-noble metal silicide, such as PtSi or Pd₂Si, for example. However, the invention may be applicable to any silicide. The high temperature treatment can be done in conventional furnace or in rapid thermal processors or flash and or spike anneal processors. The treatment temperature and time are adjusted as required for different silicidation metals. The ambient used during heat treatment can be neutral, oxidizing or reducing, depending on selection of a particular silicidation metal.

In FIG. 11, an etch 1100 is performed to remove the non-silicided metal 1002, where the etch chemistry depends on the chemical composition of the silicide layer.

In FIG. 12, a metal 1200 (typically comprised of a diffusion barrier metal and/or adhesion metal layer 1201 and some form of high conductivity filler metal 1202 such as aluminum (Al) or copper (Cu), for example) is deposited to form a contact for the anode. A Ti-based metal or TiN compound or their combination are examples of barrier metals commonly used in the industry.

Those skilled in the art to which the invention relates will appreciate that other embodiments and modifications are possible within the scope of the claimed invention. 

What is claimed is:
 1. An unguarded Schottky barrier diode comprising: a dielectric layer formed over a silicon cathode with a window opening formed in the dielectric layer through which a portion of the silicon cathode is exposed; a recessed region formed in the silicon cathode through the window opening having a central portion onto which the window opening opens, and having a peripheral etched undercut portion spaced below the window opening and extending laterally undercutting the dielectric layer; a silicide formed in substantial conformity within the recessed region including in the peripheral portion undercutting the dielectric layer; and an anode contact formed in electrical communication with the silicide formed within the central portion of the recessed region and separated by an undercut part of the dielectric layer from the silicide formed within the peripheral portion of the recessed region, wherein the sidewalls of the window are concave, wherein a tail of the dielectric layer which is also concave extends beyond an interface of the dielectric interface and the cathode, and wherein the tail is further sandwiched between the silicide layer and a diffusion metal layer to separate the diffusion metal layer from silicide within the peripheral portion of the recessed region; thereby preventing the formation of a metal-insulator-semiconductor diode, wherein no other layers are interposed between the cathode and dielectric layer and the tail of the dielectric layer.
 2. The unguarded Schottky barrier diode of claim 1, wherein the dielectric layer comprises a continuous material.
 3. The unguarded Schottky barrier diode of claim 1, wherein the sidewalls of the window are substantially vertical.
 4. The unguarded Schottky barrier diode of claim 1, wherein the silicide layer has a top silicide surface that is between a recessed surface of the recessed region and the dielectric interface surface.
 5. The unguarded Schottky barrier diode of claim 1, further comprising a filler metal that overlies the diffusion barrier layer and fills the window.
 6. The unguarded Schottky barrier diode of claim 1, further comprising a highly conductive buried layer over which the cathode extends.
 7. The unguarded Schottky barrier diode of claim 1, wherein the silicide layer undercuts the dielectric layer by approximately 10-100 nm.
 8. The unguarded Schottky barrier diode of claim 1, wherein the diffusion metal layer conformally overlies the tail of the dielectric layer and the sidewalls of the window. 